Datasheets of input devices state a setup and hold time for the data referenced to the clock. Both provided by and FPGA.
What I don't quite understand is how the FPGA complies to these values.
I assumes that the internal clock in the FPGA (which connects to to the flip-flops) is a lot faster then the clock it uses to sync with another device. Otherwise you would not be able to have a setup time as this is the time which the data should be stable before a clock edge.
Or is the same clock used and the input devices uses a next cycle to read the data like in the pictures below?
What is this clock to data relation from an output perspective called? For input this is setup and hold time.
