General Discussions

[StudentOfNUZP]

Does it make sense to compare SDAccel Development Environment and Vivado HLS to generate HDL from С++ for programming FPGA? Either do both environments use the same HLS tool to generate HDL from С++?

[goodplay]

For Xilinx product/software queries, better to ask at https://www.xilinx.com/support.html

[StudentOfNUZP]

I caught You. But I can't ask a question there because of the Export Compliance error. Also, I can't delete the current topic.

[StudentOfNUZP · Accepted solution]

I solved the issue myself.

From the following quote can be understood that SDAccel is an environment, but the Vivado HLS – a tool. Also, Vivado HLS tool are used in SDAccel and SDSoc environments.
Therefore, comparing SDAccess with Vivado HLS is incorrect, because SDAccel includes Vivado HLS.

Quote from document "UG1253 - SDx Pragma Reference Guide (v2019.1)": "In both SDAccel™ and SDSoC™ development environments, the hardware kernel must be synthesized from the OpenCL™, C, or C++ language into the register transfer level (RTL) that can be implemented into the programmable logic of a Xilinx® device. The Vivado® High-Level Synthesis (HLS) tool synthesizes RTL from the OpenCL, C, and C++ language descriptions". Source (page 51, 1st paragraph): https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2019_1/ug1253-sdx-pragm....