General Discussions

[HEMANTHKUMAR]

Hi Team,

               I have designed the PCIe Gen2 compactible System(board) with Artix 7   XC7A200T-2FFG1156C FPGA.  Board is detected in PCIe Gen1 x4 and we are able to do read and write. Now Problem is, Board is not detected for PCIe Gen2- X4 but board is detecting PCIe Gen 2- X2(not able to do read and write).

Thier was mistake in design were VTT and VCC got shorted as shown in the image. But were able to remove the short by masking pin ball and remove ball pin for AJ22, AL13 and AL15

Can anyone provide us suggestions, how to proceed? 

Below image PCIe fingers connection to FPGA MGT Bank

Thanks

Hemanth 

[goodplay · Accepted solution]

Probably better to ask at https://www.xilinx.com/support.html