AMD’s Entire Epyc ‘Rome’ Product Stack Just Leaked
Whoops. The Eurasian Economic Commission has accidentally leaked AMD’s entire upcoming Rome product stack. While we don’t know the CPUs clock speeds yet, the data revealed shows model numbers, core counts, and TDPs. If true, AMD plans to expand the total number of SKUs it offers. Currently, the company sells 14 different Epyc CPUs. There’s a single 200W SKU (Epyc 7371, 32C/64T, 3.1GHz base, 3.8GHz boost), and one 120W SKU (Epyc 7251, 8C/16T, 2.1GHz base, 2.9GHz boost). Most current Epyc CPUs have a TDP between 150-180W.
With that in mind, here’s the newly leaked data. We’ve highlighted a few of the more interesting SKUs in bold.
There are a few interesting data points here. First, the Epyc 7702P. AMD’s lowest-TDP 64-core CPU squeezes into a 200W dissipation window. While TDP is not power consumption and cannot be treated as a proxy for it, Intel’s Cascade Lake-AP CPUs have a 250W TDP for the 32-core parts, 350W for the 48-core, and 400W on the 56-core CPU. Obviously, we can’t begin to compare performance without knowing something of frequency, but the benefits of 7nm are plain to see.
The Epyc 7282 is another interesting CPU. Previously, AMD’s only 120W Epyc was an 8-core chip. Now the company has managed to squeeze 16 cores into the same thermal dissipation envelope, even in its full server form factor with eight-channel memory support.
As for the bottom-end eight-cores, AMD apparently saw enough demand for the Epyc 7251 (the single 120W 8-core SKU on 14nm) for it to be worth their while to build an explicit single-socket and multi-socket variant of that core on 7nm.
It’ll be very interesting to see how AMD’s formal power consumption figures come out against Intel this time around. If I had to guess, I’d guess that the reason we don’t see a more dramatic reduction in TDPs is for one of two reasons. Either AMD opted to use its TDP headroom in its server parts to aggressively chase frequency improvements, or it left itself plenty of thermal space for the increased heat of AVX2 workloads.
Ever since it announced Rome, AMD has been talking up how its new Epyc CPUs offer 4x the floating point, thanks to packing 2x the cores and offering full support for 256-bit AVX2 (previously AMD supported AVX2 but used 128-bit registers). It’s true that this works out to a hypothetical 4x increase in floating-point performance, but it also works out to a hefty chunk of additional power consumption. AMD has already told us that its consumer parts do not reduce their CPU clocks by a flat percentage to deal with AVX code the way that Intel CPUs do, but it’s still possible that Rome CPUs do take this step, even if Ryzen cores do not. Regardless, it would make sense for AMD to leave itself some thermal legroom, either for higher clocks or to address thermal hotspots.
AMD has not given a firm launch date for its Rome CPUs yet. They are expected in-market before the end of 2019.