EPYC Discussions

[zuno]

Hi. I'm Ryzen 5950X user.

AFAIK, Zen3 Server processor have L1 stream, L2 stream, L1 Region, L1 Stride, L2 Up/Down Prefetcher.(Software Optimization Guide for AMD EPYC 7003 processors 2.12.1(p48))

and also can control prefetcher by setting MSR register(MSRC000_0108).

So, My question is

1. Is Zen3 Desktop processor have L1 Region, L1 Stride, L2 Up/down Prefetcher?

2. Whatever, Can I get link related?

[cyring]

Have a look to the CoreFreq developments of the Cache Prefetchers