Drivers & Software

[rajanbedi123]

Hello,

When I connect a DDR4 memory to the Versal ACAP, is there a recommended pin assignment between the FPGA and memory to allow Xilinx IP to control the DDR4, or can the address, control and data signals be assigned randomly  to banks 700, 701 and 702?

Thank you

[elstaci]

Try posting your thread at Xilinx Forums (AMD). That would be the best place to have someone answer your question: https://support.xilinx.com/s/topiccatalog?language=en_US