I have attached the screenshot of my output for my simple circuit, I am getting Z in x1 & x2, and I have used a gate-level model. kindly let me know the error y I am getting like this.
Test Bench
module strucleltb();
reg a,b,c,d;
wire y,x1,x2;
struclel dut(.a(a),.b(b),.c(c),.d(d),.y(y));
initial
begin
a=0;b=1;c=1;d=1;
#10 a=1; b=1; c=0; d=0;
#15 a=0; b=0; c=0; d=0;
end
endmodule
Code
module struclel(a,b,c,d,y);
input a ,b,c,d;
output y;
wire x1,x2;
and g1(x1,a,b);
and g2(x2,c,d);
or g3(y,x1,x2);
endmodule
