In kernel module, I set MTRR (Memory Type Range Register) and PTE (Page Table Entry) as write-back cache, referring to AMD System Programming manual. (https://developer.amd.com/wordpress/media/2012/10/24593_APM_v21.pdf)
But the write request is sent to FPGA as only word size (4byte).
Unlike write, the read request is sent to the FPGA with cache block size (64 bytes) as if it were a write-through cache.
So I wonder if it does not support write-back cache.
I would appreciate your advice.
Gyeong Il Min edits the message. My system is follow: - OS: Ubuntu 16.04 - CPU: Ryzen 7 1700 - Motherboard: ASRock X370 Taichi - MMIO device: Xilinx Kintex7 Evaluation FPGA board (KC705)