Memory interleaving is a technique that CPUs use to increase the memory bandwidth available for an application. Without interleaving, consecutive memory blocks, often cache lines, are read from the same memory bank. So software that reads consecutive memory will need to wait for a memory transfer to complete before starting the next memory access. With memory interleaving enabled, consecutive memory blocks are in different banks and so can all contribute to the overall memory bandwidth a program can achieve.
EPYC CPUs are constructed with four integrated circuits, called dies, in one SoC (System on Chip) and occupy one socket. Each die has two memory controllers so that one socket has eight memory controllers. While there are multiple interleave methods supported by EPYC, they are only active when the memory controllers involved have memory DIMMs they are controlling. The default for many EPYC system vendors is called channel interleaving and will interleave between the two memory controllers in a die. Thus there can be a maximum of four interleave pairs in a socket. With eight DIMMs installed this will be the best performance achievable for many applications.