Server Processors

[t1mch0w]

Hi, I'm new to AMD processor. My processor is AMD EPYC 7452 32-Core Processor.

I have two questions: 

1) I try to get the number of L3 cache miss.

I read PPR for AMD Family 17h Models 01h,08h B2 and found the corresponding EventSelect is 0x06 and UnitMask should be 0x01. Therefore, the last four-byte of L3 cache miss should be 0x0106. I found on page 161 (PPR), the last four bytes of recommended L3 cache miss is 0x0106, as well. I think PPR supports my idea.

However, I check the events in uPprof (AMDuProf_Linux_x64_3.3.462/bin/Data/Events/) and found that the event of L3 cache miss is 0xb006.

Which one is right? Do I miss anything?

2) I want to leverage L2I PMC to get more PMC at the same time. However, I did not find any introductions to the events of L2I PMC. Does EPIC implement any L2I PMC event?

Thanks,
Fang

[swarup]

Hi @t1mch0w ,

1. L3 events used in the Events file (e.g. 0xb006) are for internal format used by uProf. You can ignore this value. You can use the events mentioned in PPR.

2. Please refer PPR document for your CPU at https://www.amd.com/en/support/tech-docs for the availability of L2 cache related PMC events.