cancel
Showing results for 
Search instead for 
Did you mean: 

Server Processors

neon
Miniboss

Is the I/O chip considered a chiplet or not?

This may seem pedantic, but I am writing something and would like to get this correct. 

Is the I/O chip in the upcoming implementation of Epyc (Rome) considered a "chiplet"? In other words, will AMD refer to Rome as an 8-chiplet design or a 9-chiplet design?

0 Likes
1 Reply
saywhut
Challenger

Well it's hard to answer that right now since there's no actual specs available to the public, but I will say that it will probably be classified as however many COMPUTE chiplets there are giving that all Rome chips will probably have the I/O die. Technically the I/O die is a chiplet, but I believe it will go based off the number of compute chiplets available.

If it's anything like Naples where all dies are active and have a total of 4 chiplets, Rome can be seen like this:

  • 8 Chiplets
  • 9 Chiplets
  • 8+1 Chiplets