Hello,
I was doing investigations around the theoretical DDR5 memory throughput of the AMD EPYC 9124 processor.
The official specification says that it supports 12 memory channels. However DDR5 specification says that "a channel" is no longer 64-bit as in the previous DDR generations, but rather 32-bit (or 32 + 😎 and that there are 2 channels per single DIMM slot. This is what got me confused, because the throughput for a single DDR5-4800 DIMM (64-bit, 2 channels) should be 38.4GB/s. Now if you multiply by 6 to get 12 channels, you get only 230.4GB/s.
The Processor specification however on the other hand also says that the available throughput per single socket is 460.8GB/s,which is double of what I have calculated. I believe the source of the issue is the channel definition - that AMD simply used the old convention "channel per dimm" and that in fact the correct value should be 24 memory channels.
Can anybody (Possibly from AMD) please clarify this?
Thank you
