AMD and Synopsys collaborate on the development of complex AI chips

Jim_Greene

Who is Synopsys?

Chip designers and manufacturers have long relied on Synopsys to provide essential tools and IP to create leading-edge silicon. Synopsys provides the EDA software that engineers use to design, simulate, and verify silicon chips. The company also provides a broad portfolio of silicon-proven semiconductor IP that can provide helpful “building blocks” that allow customers to avoid having to build/rebuild industry standard interface or common design components. These “pre-built circuits” allow designers to integrate a range of proven and standards-compliant interfaces, such as memory, Ethernet, USB, and the new Universal Chiplet Interconnect Express™ (UCIe™) standard, enabling them focus on their proprietary technology, such as compute, graphics or tailored acceleration IP.

Synopsys also offers a line of system design, verification and validation products, including tools for architecture exploration, early software development, and verification and validation of combined hardware and software systems. These tools and technologies “play a mission-critical role enabling customers such as AMD to implement (their) innovation in advanced chip development,” Koelling said.

Four Driving Forces Behind Synopsys’ Deployment of “AI to Build AI”

Koelling highlighted that the semiconductor industry is now facing a new era of pervasive intelligence – an era defined by AI proliferating to devices from cloud to edge, from automotive to PCs to smartphones. These devices are driven by software requirements to optimize performance and power for a particular workload, creating software-defined systems.

Within this new era are four driving forces that have propelled Synopsys to begin integrating AI technologies in its tools to help build customers build new AI technologies, as Koelling put it, to address the plethora of unprecedented challenges intrinsic in this new age. Those challenges are:

Fast-growing semiconductor and packaging complexity – AMD’s Instinct MI300X AI Accelerator, for example, was built using 153 billion transistors. This high transistor count further necessitates the trend towards building complex chips from an optimized assortment of smaller chips integrated into a single package (as AMD has been doing with its “chiplet” architecture for multiple AMD EPYC processor generations.). The Instinct MI300X combines accelerator chiplets, IO chiplets, and 3D stacks of High Bandwidth Memory 3 (HBM3) into a single, multi-die package.
Software complexity – such as exponential growth of large language models (LLMs) and massive data sets driving the need for more computation, more memory and faster IO.
Compressed design cycles – because AI is changing so fast, semiconductor and systems companies have sped up AI chip design cycles from 18- to 24- months to 12 months to keep pace.
Power and energy efficiency – A study published by the International Energy Agency earlier this year estimates that power for data centers, AI, and crypto mining around the world will double from 2022 to 1,000 TWhs by 2026.¹

To address these challenges, Synopsys is incorporating AI functions in their software and tools to deliver better results, faster. The company has pioneered incorporating AI capabilities into its Synopsys.ai™ EDA suite, Koelling said. As an example, when a customer is building silicon chips, Synopsys provides reinforcement learning, or RL, for design optimization – training on the fly throughout the design process with interaction from the user to optimize the design. As another example, Synopsys has developed Synopsys.ai Copilot – an AI coach for design engineers to guide along the way, provide ideas and save them time looking up information.

According to Mark Papermaster, CTO and Executive Vice President at AMD, early deployments of the Synopsys.ai EDA suite at AMD are already delivering key PPA (power, performance and area) and productivity improvements.²The next opportunity, Koelling said, could be to increase the use of generative AI to explore new spaces and create variants and options as part of the silicon design process.

Increasing Semiconductor Packaging Complexity in the age of AI

As chips become larger and more complex to meet modern demands, they are reaching what’s called the reticle limit for each die, Koelling said.

“They're just getting so large, such that customers have to break them into multiple die or what the industry is now calling chiplets within a single package,” Koelling said. “Now that creates challenges such as, ‘How do we connect them and get them to talk to each other?’”

The industry is rallying around a new interconnect standard called UCIe – Universal Chiplet Interconnect Express, for which Synopsys provides IP. “But designers face challenges with power distribution between the chips and the thermals between the chips, as well as the signal integrity as the chips talk to each other,” Koelling said. To help with this, Synopsys has a product called 3DIC Compiler that helps customers to manage these types of complexities.

AMD has been a longtime leader in this space, with its field programmable gate arrays (FPGAs), which were the first type of silicon products to take advantage of the multi-die approach. Today, the AMD Instinct MI300X utilizes 8 accelerator chiplets plus 4 IO chiplets, connected via an interposer using TSMC Chip-on-Wafer-on-Substrate (CoWoS^®) packaging technology.

3D Stacking High Bandwidth Memory

High performance processors and accelerators increasingly have multiple compute units – or cores – within them. For example, the AMD Instinct MI300X has 304 compute units that have to stay fed with data. High bandwidth memory (HBM) offers a solution to address these memory bandwidth requirements. “HBM is very high speed with a very dense interconnect,” Koelling said. “And it's typically stacked in what we call 3D stacking.” To meet these memory bandwidth demands, the AMD Instinct MI300X uses 8 stacks of HBM3 memory to provide a total of 192GB dedicated memory capacity.

Synopsys’ Hardware-Assisted Verification Systems…Built on AMD FPGAs

In a longstanding relationship with AMD since Synopsys first started their HAV product line 20 years ago, the two companies collaborate on not only integrating AMD FPGAs as the basis of Synopsys’s prototyping and emulation hardware platforms, but also the compilers used to translate the design-in-process optimally to an FPGA netlist. Synopsys’ HAV product solutions span HAPS prototyping systems used by engineers to develop new IP or subsystems on a lab benchtop, to mainstream SoC prototyping and emulation with rack-level ZeBu® EP systems, to stringing together up to 32 high-capacity ZeBu Server 5 racks for the largest silicon designs. Using these high-performance, high-reliability systems, engineers can catch tricky corner case anomalies, profile and tune the power consumption using the ZeBu Empower option, and run billions of cycles of actual workload software over the course of hours, days, or weeks before silicon arrives.

Multiple Dials to Optimize Power and Energy Efficiency

An OpenAI ChatGPT query consumes an estimated roughly 10X more power than a standard Google search³. “This (power) is something we definitely keep an eye on and help the customer optimize throughout the design process,” Koelling said. It starts with architecture exploration with the different elements of the chip. Then Synopsys enables customers to examine the workload characteristics to determine and address hotspots. At the emulation stage, ZeBu Empower offers power profiling in the context of the chip design and the software workload. “Our customers have seen 95-97% accuracy between the emulation and actual silicon,” Koelling said. “It really gives customers a good handle on the design at that stage and how to optimize and meet the power targets.” To finish everything off, Synopsys offers their PrimePower tool which offers the highest accuracy to make sure everything is functioning correctly, as expected, before final design signoff. “You really give a lot of knobs to adjust,” Greene summarized.

Measuring Success

Synopsys has many ways to measure success, including their customers’ PPA – the power performance and area metric, as well as compile times – but ultimately their goal and most important success metric is shortening development cycles for their customers and helping achieve the best product quality possible.

As a recent highlight of the collaborative success between the two companies, Synopsys’ tools and technology helped AMD build its Instinct MI300 GPU, which was recognized by AMD CEO, Lisa Su, at the AMD Advancing AI 2024 event as the fastest ramping product in AMD history!

Driving Semiconductor Advancement Forward

In our AI-driven world, Synopsys is helping semiconductor and systems companies keep pace with rapid innovation cycles. From reinforcement learning to copilot assistance, Synopsys is integrating AI capabilities into its EDA suite, reducing semiconductor design time and increasing engineer productivity. With its proven track record, including achievements with industry leaders like AMD, Synopsys is positioned to continue driving the semiconductor market forward as it continues to tackle emerging silicon, packaging and software-defined-system design, verification and validation challenges head-on.

To learn more about the tools and technologies discussed here, visit synopsys.com.

International Energy Agency Electricity 2024 - Analysis and forecast to 2026
Partnering to Drive Multi-Die Innovation Forward Video, Mark Papermaster, AMD CTO and Executive Vice President
International Energy Agency Electricity 2024 - Analysis and forecast to 2026