below is excerpt from this article, they had exact same result for 3700x
“This is an expected result. Client workloads do very little pure writing, so the CCD/IOD link is 32B/cycle while reading and 16B/cycle for writing. This allowed us to save power and area inside the package to spend on other, more beneficial areas for tangible performance benefits.”
In short, the pathway from the chiplet to the memory controller for the write data has been cut in half. This explains why it wasn’t noticeable when testing the Ryzen 9 3900X since it has two pathways to the controller, one from each chiplet so the results appeared normal. It was apparent from all the testing that this decision on the part of AMD had no noticeable effect on expected performance.
This is pretty much an expected result. The link between the Core die and IO die only writes at 16B/cycle, so you will see half the bandwidth that the 2000/1000 series hand. Also, because the IO and core dies are now separate, there is added latency when communicating with RAM, as the signal now has to pass from the core die to the IO die, and then to memory.
All the single chiplet Ryzen 3000 series chips have this lower write speed. The double chiplet versions (3900X and 3950X) are not affected, as they have two chiplets which can pass data to the IO die simultaneously.
In reality, this won't really affect performance much, as the 3000 series double the available L3 cache to compensate for the higher memory latency. The system will read/write from RAM far less often, so you have a net performance gain.
Just to expand on this though. The rate at which all 3000 series write to RAM is influenced by Infinity fabric speed, as that is what links the CCD and IOD together. Infinity fabric runs at the same speed as RAM up to 3733 MHz, so faster memory also means faster communication. After 3733 MHz to the fabric switches to a 2:1 ratio with RAM speed so that probably isn't recommended.