Recently I wanted to use perf to view cache miss state of codes. Then I refered to my [cpu PPR doc] ( my cpu amd ryzen r7 4800h can be [checked here], it is Renoir design.) and part of the [linux source codes]. But it seems that they all not offer detailed information about "Miscellaneous events" list. The doc says in `PMCx060` description:
> Bits Description
> 0 Group2. Read-write. Reset: 0. Miscellaneous events covered in more detail by Core::X86::Pmc::Core::L2RequestG2 (PMCx061).
Then I read the [OSRR(Open-Source Register Reference) for 17h family] (although the file name is "... Models 00h-2Fh"), it says about `PMCx060`:
> 0 OtherRequests. Read-write. Reset: 0. Events covered by Core::X86::Pmc::Core::L2RequestG2.
But about `PMCx061` it says:
> 7 Group1. Read-write. Reset: 0. All Group 1 commands not in **unit0**.
Amd seems to not offer 17h family BIOS and KernelDeveloper’s Guide (BKDG) doc, the latest is [16h][5]. And it isn't compatible because it only has one `L2IPMCx060` and says "L2IPMCx060 Command Related to Victim Buffers".
Q: What does "unit0" mean?
Does it mean that unitmask is 0? If so, it seems weird.