PC Processors

[cycleback]

Are there any official specifications from AMD of the memory bandwidth of the Threadripper Pro processors? Lenovo has released their P620 Thinkstations which features these processors. I can't find any official specifications for the memory bandwidth from AMD or Lenovo.

The only information I could find talking about the memory bandwidth of the Threadripper Pro processors was from CPU world but nothing official from AMD.

https://www.cpu-world.com/CPUs/Zen/AMD-Ryzen%20Threadripper%20PRO%203955WX.html

My workloads are a combination of software that requires both high CPU clock speeds and memory bandwidth (CFD & FEA).

There are Epyc processors with 8 memory channels but reduced memory bandwidths hence my concern.
https://www.servethehome.com/amd-epyc-7002-rome-cpus-with-half-memory-bandwidth/
For instance the Epyc 7252 has 8 memory channels but only a memory bandwidth of 85.3 GB/s (https://www.amd.com/en/products/cpu/amd-epyc-7252) compared to say an Epyc 7302 (https://www.amd.com/en/products/cpu/amd-epyc-7302) with a memory bandwidth of 204.8 GB/s.

[arg1]

I was just wondering this too.   

I suspect the Threadripper Pro 12-core 3945WX and the 16-core 3955WX are contructed like the Epyc 7272 and 7282 that have 4 memory channels from the SoC I/O controller to the cores rather than 8 because of having 4(2?) CCDs per package instead of 8(4?).

I believe that all of these SKUs having a L3 cache size of 64 MB is the evidence.

I just wish I could find reference material from AMD that describes if this is the case.

[elstaci]

If you haven't yet then check AMD's Technical Documentation webpage from here: https://www.amd.com/en/support/tech-docs

[arg1]

Something I came to understand recently is that the Epyc memory bandwidth of 204.8 GB/s is an aggregate value.

The maximum thoughput of a single thread on a core is governed by the Level 3 cache link which is roughly 25 GB/s to memory and 22 GB/s to PCIe (if the infinity fabric is operating at 1600 MHz).    Reaching max throughput for a thread would also require the other cores in a CCX to not interfere.