Hi,
I have an external ADC that sends 800Mbps DDR serial LVDS data along with 400MHz LVDS dco clock to the FPGA. The clock and data are phase-aligned and their tracks on the PCB are also matched-length. So the serial data and the dco clock are arrived phase-aligned at the FPGA pins.
In the FPGA, the LVDS serial data input to an IBUFDS then the output of the IBUFDS goes to an IDDR primitive. Also, the LVDS clock connect to a IBUFDS and its output goes to a BUFR. Then the output of the BUFR is used as clock of the IDDR primitive.
Based on the timing analysis, the time for generating data for IDDR is 0.7 ns, however the clock reaches to IDDR clock pin after 2.4 ns. Therefore, the timing is not met. Although this is a kind of source synchronous system but I did not defined constraint for set_input_delay.
My questions are:
How can I define set_input_delay constraint for DDR data?
Can I use IDELAYE2 to make extra delay for the data path between IBUFDS and IDDR data pin?
Can I handle this problem with constraint without instantiating IDELAYE2?
