Hello,
I develop ultra-high-performance vectorized algorithms and need to understand how the AMD processors execute instructions under the hood to take full advantage of all the optimization opportunities. I am mainly interested in the AVX-512 implementation details, multicore synchronization and cache implementation details. Getting early access to the new AMD hardware would also be a huge advantage. For the same reason, I am interested in AMD GPUs for GP GPU applications. I am willing to sign an NDA on behalf of the company I own.
As this is the only forum I am allowed to write on now, could someone from AMD guide me w.r.t. further steps?
Best regards, Piotr
