Hi
asrock a320m hdv r3
Cannot solve this problem
when there is no load pc works fine
but in 3dmark bench tests freezes after 10 to 30 seconds
nothing is overclocked
bought it new from ebay germany
updated bios
updated amd chipset
latest rtx drivers
etc
is this cpu defective?
How do I hard throttle to stock 3.7 Ghz?
I need to disable auto boost right?
PSU 700 Watt
Please help
logs are here log.zip
here is temp logs hwinfo64 https://drive.google.com/open?id=1tjioVMMy76EsaT7_dhARexZYLTbQr4Wd
specs https://drive.google.com/open?id=1XZUTJcdlc3zmiqG3xRCXY-vVuVVcdTL5
temp logs and stats are here https://drive.google.com/open?id=1r2xUtCTWQ0AyW0-qwPSO-0JYSrGMSHGW
AMD Ryzen 7 2700X
[General Information]
Processor Name: AMD Ryzen 7 2700X
Original Processor Frequency: 3700.0 MHz
Original Processor Frequency [MHz]: 3700
CPU ID: 00800F82
Extended CPU ID: 00800F82
CPU Brand Name: AMD Ryzen 7 2700X Eight-Core Processor
CPU Vendor: AuthenticAMD
CPU Stepping: <AMD Zen/Pinnacle Ridge>
CPU Code Name: Pinnacle Ridge
CPU Technology: 12 nm
CPU Thermal Design Power (TDP): 105.0 W
CPU Max. Junction Temperature (Tj,max): 85 °C
CPU Platform: AM4
Microcode Update Revision: 800820B
SMU Firmware Revision: 43.20.0
Number of CPU Cores: 8
Number of Logical CPUs: 16
[Operating Points]
CPU HFM (Base): 3700.0 MHz = 37.00 x 100.0 MHz
CPU Boost Max: [Unlimited]
CPU Current: 4091.2 MHz = 41.00 x 99.8 MHz @ 1.3438 V
CPU Bus Type: UMI
[Cache and TLB]
L1 Cache: Instruction: 8 x 64 KBytes, Data: 8 x 32 KBytes
L2 Cache: Integrated: 8 x 512 KBytes
L3 Cache: 2 x 8 MBytes
Instruction TLB: Fully associative, 64 entries
Data TLB: Fully associative, 64 entries
Row: 0 - 8 GB PC4-19200 DDR4 SDRAM Team Group TEAMGROUP-UD4-2400 |
|
| | |
[General Module Information] | | |
| Module Number: | 0 |
| Module Size: | 8 GBytes |
| Memory Type: | DDR4 SDRAM |
| Module Type: | Unbuffered DIMM (UDIMM) |
| Memory Speed: | 1200.5 MHz (DDR4-2400 / PC4-19200) |
| Module Manufacturer: | Team Group |
| Module Part Number: | TEAMGROUP-UD4-2400 |
| Module Revision: | 0.0 |
| Module Serial Number: | 134480897 |
| Module Manufacturing Date: | Year: 2018, Week: 51 |
| Module Manufacturing Location: | 0 |
| SDRAM Manufacturer: | SpecTek |
| Error Check/Correction: | None |
| | |
[Module Characteristics] | | |
| Row Address Bits: | 16 |
| Column Address Bits: | 10 |
| Module Density: | 8192 Mb |
| Number Of Ranks: | 1 |
| Device Width: | 8 bits |
| Bus Width: | 64 bits |
| Die Count: | 1 |
| Module Nominal Voltage (VDD): | 1.2 V |
| Minimum SDRAM Cycle Time (tCKAVGmin): | 0.83300 ns |
| Maximum SDRAM Cycle Time (tCKAVGmax): | 1.50000 ns |
| CAS# Latencies Supported: | 11, 12, 13, 14, 15, 16, 18 |
| Minimum CAS# Latency Time (tAAmin): | 13.320 ns |
| Minimum RAS# to CAS# Delay (tRCDmin): | 13.320 ns |
| Minimum Row Precharge Time (tRPmin): | 13.320 ns |
| Minimum Active to Precharge Time (tRASmin): | 32.000 ns |
| | |
| Supported Module Timing at 1200.0 MHz: | 16-16-16-39 |
| Supported Module Timing at 1066.1 MHz: | 15-15-15-35 |
| Supported Module Timing at 1000.0 MHz: | 14-14-14-32 |
| Supported Module Timing at 933.3 MHz: | 13-13-13-30 |
| Supported Module Timing at 866.7 MHz: | 12-12-12-28 |
| Supported Module Timing at 800.0 MHz: | 11-11-11-26 |
| | |
| Minimum Active to Active/Refresh Time (tRCmin): | 45.375 ns |
| Minimum Refresh Recovery Time Delay (tRFC1min): | 350.000 ns |
| Minimum Refresh Recovery Time Delay (tRFC2min): | 260.000 ns |
| Minimum Refresh Recovery Time Delay (tRFC4min): | 160.000 ns |
| Minimum Four Activate Window Delay Time (tFAWmin): | 21.000 ns |
| Minimum Active to Active Delay Time - Different Bank Group (tRRD_Smin): | 3.299 ns |
| Minimum Active to Active Delay Time - Same Bank Group (tRRD_Lmin): | 4.900 ns |
| Minimum CAS to CAS Delay Time - Same Bank Group (tCCD_Lmin): | 5.000 ns |
| | |
[Features] | | |
| Module Temperature Sensor (TSOD): | Not Supported |
| Module Nominal Height: | 31 - 32 mm |
| Module Maximum Thickness (Front): | 1 - 2 mm |
| Module Maximum Thickness (Back): | <= 1 mm |
| Address Mapping from Edge Connector to DRAM: | Standard |
Row: 1 - 8 GB PC4-19200 DDR4 SDRAM Team Group TEAMGROUP-UD4-2400 |
|
| | |
[General Module Information] | | |
| Module Number: | 1 |
| Module Size: | 8 GBytes |
| Memory Type: | DDR4 SDRAM |
| Module Type: | Unbuffered DIMM (UDIMM) |
| Memory Speed: | 1200.5 MHz (DDR4-2400 / PC4-19200) |
| Module Manufacturer: | Team Group |
| Module Part Number: | TEAMGROUP-UD4-2400 |
| Module Revision: | 0.0 |
| Module Serial Number: | 2164458497 |
| Module Manufacturing Date: | Year: 2018, Week: 51 |
| Module Manufacturing Location: | 0 |
| SDRAM Manufacturer: | SpecTek |
| Error Check/Correction: | None |
| | |
[Module Characteristics] | | |
| Row Address Bits: | 16 |
| Column Address Bits: | 10 |
| Module Density: | 8192 Mb |
| Number Of Ranks: | 1 |
| Device Width: | 8 bits |
| Bus Width: | 64 bits |
| Die Count: | 1 |
| Module Nominal Voltage (VDD): | 1.2 V |
| Minimum SDRAM Cycle Time (tCKAVGmin): | 0.83300 ns |
| Maximum SDRAM Cycle Time (tCKAVGmax): | 1.50000 ns |
| CAS# Latencies Supported: | 11, 12, 13, 14, 15, 16, 18 |
| Minimum CAS# Latency Time (tAAmin): | 13.320 ns |
| Minimum RAS# to CAS# Delay (tRCDmin): | 13.320 ns |
| Minimum Row Precharge Time (tRPmin): | 13.320 ns |
| Minimum Active to Precharge Time (tRASmin): | 32.000 ns |
| | |
| Supported Module Timing at 1200.0 MHz: | 16-16-16-39 |
| Supported Module Timing at 1066.1 MHz: | 15-15-15-35 |
| Supported Module Timing at 1000.0 MHz: | 14-14-14-32 |
| Supported Module Timing at 933.3 MHz: | 13-13-13-30 |
| Supported Module Timing at 866.7 MHz: | 12-12-12-28 |
| Supported Module Timing at 800.0 MHz: | 11-11-11-26 |
| | |
| Minimum Active to Active/Refresh Time (tRCmin): | 45.375 ns |
| Minimum Refresh Recovery Time Delay (tRFC1min): | 350.000 ns |
| Minimum Refresh Recovery Time Delay (tRFC2min): | 260.000 ns |
| Minimum Refresh Recovery Time Delay (tRFC4min): | 160.000 ns |
| Minimum Four Activate Window Delay Time (tFAWmin): | 21.000 ns |
| Minimum Active to Active Delay Time - Different Bank Group (tRRD_Smin): | 3.299 ns |
| Minimum Active to Active Delay Time - Same Bank Group (tRRD_Lmin): | 4.900 ns |
| Minimum CAS to CAS Delay Time - Same Bank Group (tCCD_Lmin): | 5.000 ns |
| | |
[Features] | | |
| Module Temperature Sensor (TSOD): | Not Supported |
| Module Nominal Height: | 31 - 32 mm |
| Module Maximum Thickness (Front): | 1 - 2 mm |
| Module Maximum Thickness (Back): | <= 1 mm |
| Address Mapping from Edge Connector to DRAM: |