I have this same issue with my 6900XT, and from what I have been able to find out, it is an issue between AMD's memory handling framework working in combination with the physical refresh constraints of each panel.
The key features are the panel's Pixel Clock (like a speed limit of each panel for pushing pixels) and the amount of Blanking used for each refresh.
The Blanking is excess pixels over and above your screen's resolution and was a technical feature of older CRT monitors where the electron beam would start and finish outside the part of the panel you could actually see and work its way down one horizontal line after another and then have to return back to the top to start the next refresh cycle. Blanking is made up of both a horizontal blanking component and a vertical blanking component. VESA specify standard Blanking values to be adopted by the panel manufacturers - called Coordinated Video Timings (CVT).
The Blanking specified by VESA is in either pixels (for horizontal blanking) or lines (vertical blanking) - rather than time. Therefore as panel refresh rates go up the physical time for each Blanking period each refresh cycle gets smaller. As I understand it, AMD's VRAM needs a Blanking period of sufficient time duration (I don't know what this is) to be able to downclock below it's maximum speed. If the Blanking time is too short, the memory won't downclock.
Compounding this issue is the fact the LCD panels don't actually need Blanking and so VESA have introduced Reduced Blanking specifications - CVT-RB and CVT-R2. These reduce the Blanking sizes (pixels and lines) below the the standard CVT Blanking specifications. What I think people are finding is that by using CRU and specifying 'LCD Standard' they are actually increasing the Blanking period from one of the Reduced Blanking timings used, e.g. from CVT-RB (fewer Blankng pixels/lines) back up to CVT (more Blanking pixels/lines). This increased Blanking now allows sufficient time the memory to downclock when idle.
OK you say, but why does it not work for me? This is where the panel's Pixel Clock comes in. As mentioned above, this is your panel's 'speed limit'. A monitor can only push as many pixels as it's maximum Pixel Clock limit will allow. The more pixels per refresh and the higher refresh rate, the higher Pixel Clock needed.
In order to push higher refresh rates, panel manufacturers can adopt a Reduced Blanking VESA standard as this reduces the total number of pixel's that need to be pushed and allow refresh rates that are under the panel's Pixel Clock maximum limit. However, as we saw above, this reduces the Blanking period time (in micro-seconds) each refresh and it may fall below the time required for the VRAM to down-clock. The issue comes about if you use CRU and opt for the 'LCD Standard', e.g. increases the Blanking period - but this increases the total number of pixels and lines, and to push this increased number of pixels at the refresh rate you want (e.g. 144Hz) results in a required Pixel Clock MHz rate which is above your panel's maximum Pixel Clock MHz specification and therefore pushes your panel out of the manufacturer's rated Pixel Clock specified limit.
As an example, my panel is an HP Z27n G2 and it's maximum Pixel Clock is only 310MHz (as read off the specification sheet). It can operate at 1440p and 60Hz with standard LCD timings - and hence downclocks the VRAM, but it uses Reduced Blanking timings to squeeze in a 75Hz refresh rate that is still below the 310 MHz maximum Pixel Clock limit. This results in my memory clock constantly running at max speed when at 75Hz as even at only 75Hz, the Reduced Blanking time is too short for my memory to downclock. If I try to use CRU and specify 'LCD standard" Blanking at 75Hz, the Pixel Clock needed would be faster than the 310MHz of my panel.
In order to run at high refresh rates and still have downclocked VRAM, panels need as a high Pixel Clock as possible as this would allow as long a Blanking time as possible (using one of VESA's standards, e.g. CVT) to give sufficient time for the VRAM to downclock.
I trust that the above makes sense and is close to reality, but I apologise for the long post and any technical mistakes I have made. I am just trying to make some sense of what I have found thus far.
