Hi,
I have the Zynq UltraScale setup as PCIe root complex, but am not able to receive a MSI0 interrupt from an Endpoint.
1. I have connected my ISR to interrupt 146 for MSI0 using the general interrupt controller.
2. Before doing the PCIe bus enumeration I enable MSI:
Xil_Out32((UINTPTR)(0xFD0E0308), 0x0001); // MSII_CONTROL REGISTER
3. I set the MSII_BASE_LO Register to: 0xFE440000 as per the documentation.
4. I set the MSI Mask Lo Register to: 0x00FF.
To what PCIe address must the remote PCIE EndPoint send its MSI message to be able to receive it on the UltraScale PCIE root complex device?
Must I configure any other registers to be able to receive MSI0 interrupts?
Thanks,
Jan.
