The number of architectural registers (ie registers visible in the programming model) needs to be stable to avoid every application needing to have a lot of different binaries, one for each generation of programming model, but the number of physical registers used at runtime has been growing regularly.
Execution, Load/Store, INT and FP Scheduling - The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X,...
Looking at Ryzen-family processors as an example, there may only be 16 architectural GPRs for integer operations, but the underlying hardware uses 168 physical registers via register renaming. On the floating point side there are more architectural registers (because that part of the ISA was developed more recently) but only 160 physical registers used at execution time.
