General Discussions

[xiaopeng1988]

vivado 2018.3 QDRII+ SRAM IP core simulation in default setting of example project is wrong, I find c0_init_calib_complete is valid very soon, but I think the memory calibration is not done, because I don't find the calibration process in data bus. And I find the read data(app interface) is not the same as the write data, the read data shift one word to the write data.

I use ISE14.7 MIG IP core(use QDRII+ SRAM) to simulate in default setting of example project, I find init_calib_complete is valid after a moment, and I think the memory calibration is done, because I find the calibration process in data bus. And I find the read data(app interface) is the same as the write data.

Who can answer that the simulation result of two platforms is not the same?

[Smart_Waves]

Hai,

I am getting this error while doing implementation after completing the synthesis successfully in vivado tool 2018.2. i am using ddr4-sdram part number is MT40A256M16GE-075B and in Ip configuration I had given 1.2 voltage and frequency also 2666ps (375 MHz). please check once given suggestion for proceed further.

I am posting my top-level code and error also

My top-level code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity ddr_sdram_wrapper is
port (
clk_in1 : in STD_LOGIC;
ddr4_rtl_act_n : out
STD_LOGIC;
ddr4_rtl_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
ddr4_rtl_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_bg : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_dm_n : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr4_rtl_dq : inout STD_LOGIC_VECTOR ( 63 downto 0 );
ddr4_rtl_dqs_c : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr4_rtl_dqs_t : inout STD_LOGIC_VECTOR ( 7 downto 0 );
ddr4_rtl_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_reset_n : out STD_LOGIC;
reset_rtl : in STD_LOGIC;
sys_clk_n : in STD_LOGIC;
uart_rtl_rxd : in STD_LOGIC;
uart_rtl_txd : out STD_LOGIC
);
end ddr_sdram_wrapper;

architecture STRUCTURE of ddr_sdram_wrapper is

signal c0_clk_in1 :STD_LOGIC;
signal c0_ddr4_act_n : std_logic;
signal c0_ddr4_adr : std_logic_vector(16 downto 0);
signal c0_ddr4_ba : std_logic_vector(1 downto 0);
signal c0_ddr4_bg : std_logic_vector (0 to 0);
signal c0_ddr4_ck_c : std_logic_vector(0 to 0);
signal c0_ddr4_ck_t : std_logic_vector(0 to 0);
signal c0_ddr4_cke : std_logic_vector(0 to 0);
signal c0_ddr4_cs_n : std_logic_vector(0 to 0);
signal c0_ddr4_dm_dbi_n : std_logic_vector(1 downto 0);
signal c0_ddr4_dq : std_logic_vector(15 downto 0);
signal c0_ddr4_dqs_c : std_logic_vector(1 downto 0);
signal c0_ddr4_dqs_t : std_logic_vector(1 downto 0);
signal c0_ddr4_odt : std_logic_vector(0 to 0);
signal c0_ddr4_reset_n : std_logic;
signal c0_sys_clk_in : std_logic;
signal c0_reset_rtl_0 : std_logic;
signal c0_uart_rtl_rxd : std_logic;
signal c0_uart_rtl_txd : std_logic;
signal c0_ddr4_1_act_n : std_logic;
signal c0_ddr4_1_adr : std_logic_vector(16 downto 0);
signal c0_ddr4_1_ba : std_logic_vector(1 downto 0);
signal c0_ddr4_1_bg : std_logic_vector (0 to 0);
signal c0_ddr4_1_ck_c : std_logic_vector(0 to 0);
signal c0_ddr4_1_ck_t : std_logic_vector(0 to 0);
signal c0_ddr4_1_cke : std_logic_vector(0 to 0);
signal c0_ddr4_1_cs_n : std_logic_vector(0 to 0);
signal c0_ddr4_1_dm_dbi_n : std_logic_vector(1 downto 0);
signal c0_ddr4_1_dq : std_logic_vector(15 downto 0);
signal c0_ddr4_1_dqs_c : std_logic_vector(1 downto 0);
signal c0_ddr4_1_dqs_t : std_logic_vector(1 downto 0);
signal c0_ddr4_1_odt : std_logic_vector(0 to 0);
signal c0_ddr4_1_reset_n : std_logic;
signal c0_ddr4_2_act_n : std_logic;
signal c0_ddr4_2_adr : std_logic_vector(16 downto 0);
signal c0_ddr4_2_ba : std_logic_vector(1 downto 0);
signal c0_ddr4_2_bg : std_logic_vector (0 to 0);
signal c0_ddr4_2_ck_c : std_logic_vector(0 to 0);
signal c0_ddr4_2_ck_t : std_logic_vector(0 to 0);
signal c0_ddr4_2_cke : std_logic_vector(0 to 0);
signal c0_ddr4_2_cs_n : std_logic_vector(0 to 0);
signal c0_ddr4_2_dm_dbi_n : std_logic_vector(1 downto 0);
signal c0_ddr4_2_dq : std_logic_vector(15 downto 0);
signal c0_ddr4_2_dqs_c : std_logic_vector(1 downto 0);
signal c0_ddr4_2_dqs_t : std_logic_vector(1 downto 0);
signal c0_ddr4_2_odt : std_logic_vector(0 to 0);
signal c0_ddr4_2_reset_n : std_logic;
signal c0_ddr4_3_act_n : std_logic;
signal c0_ddr4_3_adr : std_logic_vector(16 downto 0);
signal c0_ddr4_3_ba : std_logic_vector(1 downto 0);
signal c0_ddr4_3_bg : std_logic_vector (0 to 0);
signal c0_ddr4_3_ck_c : std_logic_vector(0 to 0);
signal c0_ddr4_3_ck_t : std_logic_vector(0 to 0);
signal c0_ddr4_3_cke : std_logic_vector(0 to 0);
signal c0_ddr4_3_cs_n : std_logic_vector(0 to 0);
signal c0_ddr4_3_dm_dbi_n : std_logic_vector(1 downto 0);
signal c0_ddr4_3_dq : std_logic_vector(15 downto 0);
signal c0_ddr4_3_dqs_c : std_logic_vector(1 downto 0);
signal c0_ddr4_3_dqs_t : std_logic_vector(1 downto 0);
signal c0_ddr4_3_odt : std_logic_vector(0 to 0);
signal c0_ddr4_3_reset_n : std_logic;

component ddr_sdram is
port (
-- Ports for each DDR SDRAM instance
clk_in1 : in STD_LOGIC;
ddr4_rtl_0_act_n : out STD_LOGIC;
ddr4_rtl_0_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
ddr4_rtl_0_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_0_bg : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_0_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_0_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_0_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_0_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_0_dm_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_0_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr4_rtl_0_dqs_c : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_0_dqs_t : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_0_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_0_reset_n : out STD_LOGIC;
ddr4_rtl_1_act_n : out STD_LOGIC;
ddr4_rtl_1_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
ddr4_rtl_1_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_1_bg : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_1_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_1_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_1_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_1_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_1_dm_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_1_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr4_rtl_1_dqs_c : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_1_dqs_t : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_1_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_1_reset_n : out STD_LOGIC;
ddr4_rtl_2_act_n : out STD_LOGIC;
ddr4_rtl_2_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
ddr4_rtl_2_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_2_bg : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_2_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_2_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_2_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_2_dm_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr4_rtl_2_dqs_c : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_2_dqs_t : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_2_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_2_reset_n : out STD_LOGIC;
ddr4_rtl_3_act_n : out STD_LOGIC;
ddr4_rtl_3_adr : out STD_LOGIC_VECTOR ( 16 downto 0 );
ddr4_rtl_3_ba : out STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_3_bg : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_3_ck_c : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_3_ck_t : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_3_cke : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_3_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_3_dm_n : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_3_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 );
ddr4_rtl_3_dqs_c : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_3_dqs_t : inout STD_LOGIC_VECTOR ( 1 downto 0 );
ddr4_rtl_3_odt : out STD_LOGIC_VECTOR ( 0 to 0 );
ddr4_rtl_3_reset_n : out STD_LOGIC;
reset_rtl_0 : in STD_LOGIC;
sys_clk_n : in STD_LOGIC;
uart_rtl_0_rxd : in STD_LOGIC;
uart_rtl_0_txd : out STD_LOGIC
);
end component ddr_sdram;

begin

ddr4_rtl_act_n <= c0_ddr4_act_n;
ddr4_rtl_adr(16 downto 0) <= c0_ddr4_adr(16 downto 0);
ddr4_rtl_ba(1 downto 0) <= c0_ddr4_ba(1 downto 0);
ddr4_rtl_bg(0 to 0) <= c0_ddr4_bg(0 to 0);
ddr4_rtl_ck_c(0 to 0) <=c0_ddr4_ck_c(0 to 0);
ddr4_rtl_ck_t(0 to 0) <=c0_ddr4_ck_t(0 to 0);
ddr4_rtl_cke(0 to 0) <=c0_ddr4_cke(0 to 0);
ddr4_rtl_cs_n(0 to 0) <=c0_ddr4_cs_n(0 to 0);
ddr4_rtl_dm_n(1 downto 0) <=c0_ddr4_dm_dbi_n(1 downto 0);
ddr4_rtl_dq(15 downto 0) <=c0_ddr4_dq(15 downto 0);
ddr4_rtl_dqs_c(1 downto 0) <=c0_ddr4_dqs_c(1 downto 0);
ddr4_rtl_dqs_t(1 downto 0) <=c0_ddr4_dqs_t(1 downto 0);
ddr4_rtl_odt(0 to 0) <=c0_ddr4_odt(0 to 0) ;
ddr4_rtl_act_n <= c0_ddr4_2_act_n;
ddr4_rtl_adr(16 downto 0) <= c0_ddr4_2_adr(16 downto 0);
ddr4_rtl_ba(1 downto 0) <= c0_ddr4_2_ba(1 downto 0);
ddr4_rtl_bg(0 to 0) <= c0_ddr4_2_bg(0 to 0);
ddr4_rtl_ck_c(0 to 0) <=c0_ddr4_2_ck_c(0 to 0);
ddr4_rtl_ck_t(0 to 0) <=c0_ddr4_2_ck_t(0 to 0);
ddr4_rtl_cke(0 to 0) <=c0_ddr4_2_cke(0 to 0);
ddr4_rtl_cs_n(0 to 0) <=c0_ddr4_2_cs_n(0 to 0);
ddr4_rtl_dm_n(3 downto 2) <=c0_ddr4_2_dm_dbi_n(1 downto 0);
ddr4_rtl_dq(31 downto 16) <=c0_ddr4_2_dq(15 downto 0);
ddr4_rtl_dqs_c(3 downto 2) <=c0_ddr4_2_dqs_c(1 downto 0);
ddr4_rtl_dqs_t(3 downto 2) <=c0_ddr4_2_dqs_t(1 downto 0);
ddr4_rtl_odt(0 to 0) <=c0_ddr4_2_odt(0 to 0) ;
ddr4_rtl_act_n <= c0_ddr4_1_act_n;
ddr4_rtl_adr(16 downto 0) <= c0_ddr4_1_adr(16 downto 0);
ddr4_rtl_ba(1 downto 0) <= c0_ddr4_1_ba(1 downto 0);
ddr4_rtl_bg(0 to 0) <= c0_ddr4_1_bg(0 to 0);
ddr4_rtl_ck_c(0 to 0) <=c0_ddr4_1_ck_c(0 to 0);
ddr4_rtl_ck_t(0 to 0) <=c0_ddr4_1_ck_t(0 to 0);
ddr4_rtl_cke(0 to 0) <=c0_ddr4_1_cke(0 to 0);
ddr4_rtl_cs_n(0 to 0) <=c0_ddr4_1_cs_n(0 to 0);
ddr4_rtl_dm_n(5 downto 4) <=c0_ddr4_1_dm_dbi_n(1 downto 0);
ddr4_rtl_dq(47 downto 32) <=c0_ddr4_1_dq(15 downto 0);
ddr4_rtl_dqs_c(5 downto 4) <=c0_ddr4_1_dqs_c(1 downto 0);
ddr4_rtl_dqs_t(5 downto 4) <=c0_ddr4_1_dqs_t(1 downto 0);
ddr4_rtl_odt(0 to 0) <=c0_ddr4_1_odt(0 to 0) ;
ddr4_rtl_act_n <= c0_ddr4_3_act_n;
ddr4_rtl_adr(16 downto 0) <= c0_ddr4_3_adr(16 downto 0);
ddr4_rtl_ba(1 downto 0) <= c0_ddr4_3_ba(1 downto 0);
ddr4_rtl_bg(0 to 0) <= c0_ddr4_3_bg(0 to 0);
ddr4_rtl_ck_c(0 to 0) <=c0_ddr4_3_ck_c(0 to 0);
ddr4_rtl_ck_t(0 to 0) <=c0_ddr4_3_ck_t(0 to 0);
ddr4_rtl_cke(0 to 0) <=c0_ddr4_3_cke(0 to 0);
ddr4_rtl_cs_n(0 to 0) <=c0_ddr4_3_cs_n(0 to 0);
ddr4_rtl_dm_n(7 downto 6) <=c0_ddr4_3_dm_dbi_n(1 downto 0);
ddr4_rtl_dq(63 downto 48) <=c0_ddr4_3_dq(15 downto 0);
ddr4_rtl_dqs_c(7 downto 6) <=c0_ddr4_3_dqs_c(1 downto 0);
ddr4_rtl_dqs_t(7 downto 6) <=c0_ddr4_3_dqs_t(1 downto 0);
ddr4_rtl_odt(0 to 0) <=c0_ddr4_3_odt(0 to 0) ;
ddr4_rtl_reset_n <=c0_ddr4_reset_n;
uart_rtl_txd <=c0_uart_rtl_txd;


ddr4_sdram_i: ddr_sdram
port map (
clk_in1 => clk_in1,
ddr4_rtl_0_act_n => ddr4_rtl_act_n,
ddr4_rtl_0_adr(16 downto 0) => ddr4_rtl_adr(16 downto 0),
ddr4_rtl_0_ba(1 downto 0) => ddr4_rtl_ba(1 downto 0) ,
ddr4_rtl_0_bg(0 to 0) => ddr4_rtl_bg(0 to 0),
ddr4_rtl_0_ck_c(0 to 0) => ddr4_rtl_ck_c(0 to 0),
ddr4_rtl_0_ck_t(0 to 0) => ddr4_rtl_ck_t(0 to 0),
ddr4_rtl_0_cke(0 to 0) => ddr4_rtl_cke(0 to 0),
ddr4_rtl_0_cs_n(0 to 0) => ddr4_rtl_cs_n(0 to 0),
ddr4_rtl_0_dm_n(1 downto 0) => ddr4_rtl_dm_n(1 downto 0),
ddr4_rtl_0_dq(15 downto 0) => ddr4_rtl_dq(15 downto 0),
ddr4_rtl_0_dqs_c(1 downto 0) => ddr4_rtl_dqs_c(1 downto 0),
ddr4_rtl_0_dqs_t(1 downto 0) => ddr4_rtl_dqs_t(1 downto 0),
ddr4_rtl_0_odt(0 to 0) => ddr4_rtl_odt(0 to 0),
ddr4_rtl_0_reset_n=> ddr4_rtl_reset_n,
ddr4_rtl_1_act_n => ddr4_rtl_act_n,
ddr4_rtl_1_adr(16 downto 0) => ddr4_rtl_adr(16 downto 0),
ddr4_rtl_1_ba(1 downto 0) => ddr4_rtl_ba(1 downto 0),
ddr4_rtl_1_bg(0 to 0) => ddr4_rtl_bg(0 to 0),
ddr4_rtl_1_ck_c(0 to 0) => ddr4_rtl_ck_c(0 to 0),
ddr4_rtl_1_ck_t(0 to 0) => ddr4_rtl_ck_t(0 to 0),
ddr4_rtl_1_cke(0 to 0) => ddr4_rtl_cke(0 to 0),
ddr4_rtl_1_cs_n(0 to 0) => ddr4_rtl_cs_n(0 to 0),
ddr4_rtl_1_dm_n(1 downto 0) => ddr4_rtl_dm_n(3 downto 2),
ddr4_rtl_1_dq(15 downto 0) => ddr4_rtl_dq(31 downto 16),
ddr4_rtl_1_dqs_c(1 downto 0) => ddr4_rtl_dqs_c(3 downto 2),
ddr4_rtl_1_dqs_t(1 downto 0) => ddr4_rtl_dqs_t(3 downto 2),
ddr4_rtl_1_odt(0 to 0) => ddr4_rtl_odt(0 to 0),
ddr4_rtl_1_reset_n=> ddr4_rtl_reset_n,
ddr4_rtl_2_act_n => ddr4_rtl_act_n,
ddr4_rtl_2_adr(16 downto 0) => ddr4_rtl_adr(16 downto 0),
ddr4_rtl_2_ba(1 downto 0) => ddr4_rtl_ba(1 downto 0),
ddr4_rtl_2_bg(0 to 0) => ddr4_rtl_bg(0 to 0),
ddr4_rtl_2_ck_c(0 to 0) => ddr4_rtl_ck_c(0 to 0),
ddr4_rtl_2_ck_t(0 to 0) => ddr4_rtl_ck_t(0 to 0),
ddr4_rtl_2_cke(0 to 0) => ddr4_rtl_cke(0 to 0),
ddr4_rtl_2_cs_n(0 to 0) => ddr4_rtl_cs_n(0 to 0),
ddr4_rtl_2_dm_n(1 downto 0) => ddr4_rtl_dm_n(5 downto 4),
ddr4_rtl_2_dq(15 downto 0) => ddr4_rtl_dq(47 downto 32),
ddr4_rtl_2_dqs_c(1 downto 0) => ddr4_rtl_dqs_c(5 downto 4),
ddr4_rtl_2_dqs_t(1 downto 0) => ddr4_rtl_dqs_t(5 downto 4),
ddr4_rtl_2_odt(0 to 0) => ddr4_rtl_odt(0 to 0),
ddr4_rtl_2_reset_n=> ddr4_rtl_reset_n,
ddr4_rtl_3_act_n => ddr4_rtl_act_n,
ddr4_rtl_3_adr(16 downto 0) => ddr4_rtl_adr(16 downto 0),
ddr4_rtl_3_ba(1 downto 0) => ddr4_rtl_ba(1 downto 0),
ddr4_rtl_3_bg(0 to 0) => c0_ddr4_bg(0 to 0) ,
ddr4_rtl_3_ck_c(0 to 0) => ddr4_rtl_ck_c(0 to 0) ,
ddr4_rtl_3_ck_t(0 to 0) => ddr4_rtl_ck_t(0 to 0) ,
ddr4_rtl_3_cke(0 to 0) => ddr4_rtl_cke(0 to 0) ,
ddr4_rtl_3_cs_n(0 to 0) => ddr4_rtl_cs_n(0 to 0) ,
ddr4_rtl_3_dm_n(1 downto 0) => ddr4_rtl_dm_n(7 downto 6),
ddr4_rtl_3_dq(15 downto 0) => ddr4_rtl_dq(63 downto 48),
ddr4_rtl_3_dqs_c(1 downto 0) => ddr4_rtl_dqs_c(7 downto 6),
ddr4_rtl_3_dqs_t(1 downto 0) => ddr4_rtl_dqs_t(7 downto 6),
ddr4_rtl_3_odt(0 to 0) => ddr4_rtl_odt(0 to 0),
ddr4_rtl_3_reset_n=> ddr4_rtl_reset_n,
reset_rtl_0 => reset_rtl,
sys_clk_n => sys_clk_n,
uart_rtl_0_rxd => uart_rtl_rxd,
uart_rtl_0_txd => uart_rtl_txd
);
end architecture;

i got this error in implementation-opt_design error

• [DRC MDRV-1] Multiple Driver Nets: Net ddr4_sdram_i/ddr4_3/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/ddr4_rtl_cke[0][5] has multiple drivers: ddr4_sdram_i/ddr4_3/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[5].genblk1.OBUF/O, ddr4_sdram_i/ddr4_1/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[5].genblk1.OBUF/O, ddr4_sdram_i/ddr4_2/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[5].genblk1.OBUF/O, and ddr4_sdram_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[5].genblk1.OBUF/O.
• [DRC MDRV-1] Multiple Driver Nets: Net ddr4_sdram_i/ddr4_3/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/ddr4_rtl_cke[0][6] has multiple drivers: ddr4_sdram_i/ddr4_3/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[6].genblk1.OBUF/O, ddr4_sdram_i/ddr4_1/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[6].genblk1.OBUF/O, ddr4_sdram_i/ddr4_2/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[6].genblk1.OBUF/O, and ddr4_sdram_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[3].u_ddr_iob_byte/genBuf[6].genblk1.OBUF/O.