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lipengfei
Journeyman III

vivado差分信号管脚约束

set_property-dict   {PACKAGE_PIN  T8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {rx_data_in_n[5]}]

set_property-dict   {PACKAGE_PIN  R8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports {rx_data_in_p[5]}]

想请教大家一下:

上面两段约束是对一个差分信号的管脚约束,其中的“PACKAGE_PIN  R8  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100”每个字符段分别代表什么含义,以及如何判断这个差分信号的电压约束大小,谢谢大家!

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There is a separate site for Xilinx support, https://www.xilinx.com/support.html

 

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