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General Discussions

yongyong
Journeyman III
‎09-28-2023 01:50 AM

segmentation fault in application execution for PS-PL AXI interface

Hi, I am a beginner with this Ultrascale+ ZCU106 board, and while I was building a program, I found that segmentation fault has been occurred.

I am now trying to test basic AXI interface between PS and PL section of the board. 

I have built the hardware design with custom IP, and built the vitis application. 

I was trying to generate begin signal and see it works in PL area.

Our AXI base address is 0xA0000000 in this code. 

I also have tried to fix something on device tree, but it still does not work. 

Here is a picture of my Vitis code, Vivado block design and the error code while executing .elf file. 

Please let me know how to solve this problem. 

block design for PS-PL AXI interface.pnglinux domain setting in vitis before create application.pngvitis code for axi.pngmemory address for PS-PL AXI interface.pngresult of build application in vitis.png

result of updating device tree for AXI custom ip.png

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goodplay
MVP
‎09-28-2023 02:48 AM

Probably better to ask at https://www.xilinx.com/support.html

My PC- Ryzen 5 5600x, B550 aorus pro ac, Hyper 212 black, 2 x 16gb F4-3600c16dgtzn kit, NM790 2TB, Nitro+RX6900XT, RM850, Win.10 Pro., LC27G55T.
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