Hello AMD Developer Community,
I am trying to calculate the Pending Request on L2 Cache or L2 MLP (Maximum Level Parallelism) on AMD EPYC 7763 64-Core Processor using the below formulae -
L2 Pending Request = L2 Cache Miss (Event[0x430964] + Event[0x431F71] + Event[0x431F72]) - L2 Refill (x165). However, L2 Cache Miss >> L2 Refill.
Does anyone know the exact formulae to calculate L2 pending requests using PMU?
