Hi,
I am currently working with a Kintex UltraScale FPGA (XCKU060-2FFVA1517I) paired with a Marvell 88E1111 PHY. We are encountering an issue where Ethernet packet transmission fails after a power cycle when the board temperature reaches 45 degrees Celsius or higher.
Here are the key observations:
The PHY link is successfully established, and the FPGA-to-board packet transmission appears to be functioning correctly within the AXI 1G/2.5G Ethernet Subsystem. (verified on ILA)
However, no packets are detected on Wireshark, indicating that the packets are not being transmitted over the physical Ethernet link.
We are using the Ethernet block design with the AXI Ethernet IP core. The issue seems to be temperature-dependent, as it does not occur at lower temperatures.
Could you please provide guidance on potential causes or debugging steps to resolve this issue? Any insights into whether this could be related to the PHY, FPGA configuration, or temperature sensitivity would be greatly appreciated.
