We were trying to implement the above code on the RFSoC 4x2 board using Vivado 2024.2 . We were successfully able to generate the bitstream with the below constraints file(.xdc) :
The bitstream is dumped into the board using JTAG/UART port. The code initially when reset is pre-applied(while programming the device) the LEDs were set to initial state as expected but the LEDs were not shifting as per the program is intended to do. Even if the reset is activated once the dumping is done, it's in vain. So it appears to us that we were not getting the 'clk' signal from board or it is stuck to some value(no transitions). We mapped the 'clk' signal to the following IO pins (in the .xdc file):
But none of them were successful.
Please suggest how to get the clk signal for the program or configure the clk. The board pic is attached for reference after the bitstream is dumped(with pre-applied reset).
