I'm trying to use Tcl to obtain detailed information about all cells (such as site location, BEL, etc.) after FPGA placement. However, for larger Verilog projects, the process is very slow. Is there any way to improve the performance?
1 Solution
@xiaodoubai wrote:
I'm trying to use Tcl to obtain detailed information about all cells (such as site location, BEL, etc.) after FPGA placement. However, for larger Verilog projects, the process is very slow. Is there any way to improve the performance?
To improve Tcl performance when extracting cell information in large Verilog projects, optimize get_property calls by retrieving multiple properties in a single call. Utilize Tcl's built-in functions like lmap for efficient list processing. Reduce hierarchy depth, consider ungrouping (with caution), and leverage caching to avoid redundant lookups. Explore parallel processing and filtering to further enhance performance. Remember to test optimizations on a smaller subset of the design before full implementation.
@xiaodoubai wrote:
I'm trying to use Tcl to obtain detailed information about all cells (such as site location, BEL, etc.) after FPGA placement. However, for larger Verilog projects, the process is very slow. Is there any way to improve the performance?
To improve Tcl performance when extracting cell information in large Verilog projects, optimize get_property calls by retrieving multiple properties in a single call. Utilize Tcl's built-in functions like lmap for efficient list processing. Reduce hierarchy depth, consider ungrouping (with caution), and leverage caching to avoid redundant lookups. Explore parallel processing and filtering to further enhance performance. Remember to test optimizations on a smaller subset of the design before full implementation.
set pin_nets [get_nets -of_objects $pins]
Why does this command not get all the nets of pins, so many nets are missing.
The following foreach command is available, but it is very slow
