"I am using the Xilinx AXI UART Lite IP in my design, and I need to access some of its internal signals (e.g., control signals or FIFO-related signals) to connect them to other modules in my top-level design. Since the IP is provided as an .xci file, I cannot directly see or modify its internal RTL code.
I want to know:
- Is it possible to bring these internal signals to the top-level ports of the IP for synthesis?
- Can the IP be edited or repackaged to expose these signals without violating design restrictions?
- If not, are there alternative methods to access or monitor these internal signals during synthesis, such as using debugging tools like ILA?
I would appreciate guidance or best practices for handling such scenarios in Vivado."
