I have a hand-me-down Xilinx project that I am studying to learn Xilinx Vivado. It utilizes components from the unisims library (ODDR, ODELAYE2, IDDR, and IDELAYE1). These components don't seem synthesizable given that there are wait statements, the GSR signal is commented out even though it is used in the definition of GSR_dly, and that there are processes that define the signals on both the positive edge and the negative edge of the clock. These are things I'm used to having my tools complain.
My understanding is that unisims is a simulation library however the design fully synthesizes with them and I can see the unisims components appear in the schematic of the synthesized design even though it looks like unsynthesizable code. Is there perhaps another definition somewhere with a synthesizable version that Xilinx just knows to look for? How can I tell what exactly is happening here?
Thank you,
