In AMD64 Architecture Programmer's Manual Volume 2: System Programming (24593) [1], chapter 15.36.18, Secure TSC, there seems to be a mistake:
> SNP-active guests may choose to enable the Secure TSC feature through SEV_FEATURES bit 9 (SecureTscEn). When enabled, Secure TSC changes the guest view of the Time Stamp Counter when read by the guest via either the TSC MSR, RDTSC, or RDTSCP instructions. The TSC value is first scaled with the GUEST_TSC_SCALE value from the VMSA and then is added to the VMSA
GUEST_TSC_OFFSET value. The P0 frequency, TSC_RATIO (C001_0104h) and TSC_OFFSET (VMCB offset 50h) values are not used in the calculation.
TSC_RATIO is C000_0104h, and not C001_0104h.
I'm not sure where to send this, but thought I'd give it a go here.
[1] https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf
