o_O
Currently DDR4 has a peak frequency of 4800MHz … Server Processors however simply do not use such., as it's important they support ECC, High Quantity and High Capacity; which means you're looking at 2100 - 3000MHz.
This suits Server Processors., given they're Highly Threaded / Core Count Processors... typically utilising most if not all of said Available Cores/Threads via Virtualised Environments with Enclosed Environment Semi-Passive Cooling Solutions.
i.e. the tend to be running at MUCH Lower Frequencies than Desktop Processors.
As they're running at Lower Frequencies (in this case 1.4GHz to 2.2GHz)., then their FSB/NB is operating at a lower frequency as well (see above) compared to Desktop.
And you think that DRAM Frequency not "Keeping Pace with Processor Frequencies"., which doesn't matter in the case of Intel as the FSB and Processor Bus are Independent of each other; and doesn't matter in the case of AMD because the NB is far below the Peak of even "Mainstream" DRAM Frequencies … but note how AMD is also quite renown for Higher Memory Bandwidth, especially with Full Population; because it has more Lanes being concurrently utilised and dispatched Asynchronously.
…
Look, your enthusiasm to engage in various technical discussions is appreciated., but your actual technical knowledge is below basic.
Now hopefully AMD has improved the Memory < > L3 Cache Latency., as well as been able to switch to a Global / Shared L3 Cache Model rather than a Local L3 Cache Model; because the issue with Epyc/Threadripper/Ryzen 1st and 2nd Gen, was that Data required for each Core Complex would trigger another direct Memory Map even IF said Data was available in another L3 Cache … this would result in a Full R+W of the Main Memory., which when you're talking about up to 60-72ns / Access Vs. 8-12ns / Access of the L3; and bare in mind that with full Saturation you're looking at up to 4 Access Calls (for the SAME Data., that would need to be Globally Shared somehow) … well I'm sure I don't have to walk you entirely through why it was possible to have up to 180 - 220ns Latency that would affect performance; as well if the Cores don't have the Data, they have to wait to do those Instructions.
If there was a Memory Bottleneck., that's where it'll likely be... especially as the Chiplet design, does introduce some.
I mean you do know that when you make such baseless statements as those in your posts., you only make yourself look like an idiot.
And I've seen this A LOT in many of your posts about various CPU / GPU Discussions.
If you actually want to learn about more technical topics., then just ask... these aren't the NVIDIA Forums, or Reddit., you're not going to be called names for not knowing something., instead you'll likely get (a couple) of decent explanations that can be used a primers to then look further into said topic for yourself.
