The PPR lists two sets of model-specific registers with overlapping addresses.
[This is almost certainly not the right place to post this, but I'd appreciate it if someone could pass this along to the technical writers so it can get fixed.]
Looking at this document: "Processor Programming Reference (PPR) for AMD Family 19h Model 21h, Revision B0 Processors", 56214-B0 Rev 3.05 - Apr 22, 2021, pages 161-162.
The IO Range Base (Core::X86__Msr__IORR_BASE) addresses are MSRC001_001[6..8]
The IO Range Mask (CORE::X86::Msr::IORR_MASK) addresses are MSRC001_001[7..9].
Those ranges overlap.
I see the same overlap occurring in an earlier document:
"Open-Source Register Reference For AMD Family 17h Processors Models 00h-2Fh", 56255 Rev 3.03 - July, 2018, pages 125-126.
Looking for hints in the Linux kernel, drivers/char/agp/nvidia-agp.c defines IORR_BASE0 as 0xC0010016 and IORR_MASK0 as 0xC0010017.
Based on that and the description of the registers ("combine to specify the two sets of base and mask pairs for two IORR ranges") I'm guessing the intended address notation is MSRC001_001[6,8] and MSRC001_001[7,9], respectively.
My questions are:
1. May I get a confirmation that the above is the correct interpretation?
2. How can I send these kinds of documentation queries directly to the tech writers? I spend more time in MSR documentation than the average bear, and there are always a few typos that don't necessarily affect correctness but could still stand to be cleaned up. Happy to send them directly without bothering folks here.
Thanks,
Barry Rountree
Center for Applied Scientific Computing
Lawrence Livermore National Laboratory
