Adaptive SoC & FPGA Discussions

[christinayao]

We utilize Alveo U200 as the PCIe Endpoint device to combine our IP and it works well with XRT.

Now, we try to migrate the environment from Alveo U200 to ZCU106 and fail to initialize our ZCU106
based on the documentation (https://github.com/Xilinx/Vitis-Tutorials/blob/2024.2/Vitis_Platform_Creation/Design_Tutorials/02-Ed... )

it seems to be  related to a failure in loading the firmware
So far, our understanding is that U200 requires a shell loading process, but since ZCU106 already has a shell, there is no need to load shell.
However, XRT driver still requires a shell to be loaded.

in current, we're facing two issues:
1. we use the same Class ID with U200 and a Vendor Specific Extended Capability (VSEC) is necessary in XRT initialization flow.
    based on the documentation (https://docs.amd.com/r/en-US/pg213-pcie4-ultrascale-plus/XVC-over-PCIe-Through-PCIe-Extended-Configu...),
    we can only provide the corresponding values for the red box through the debug bridge, but we have not yet figured out how to provide the values for the green box.
    it cause the lack of information to initialize the platform.

2. due to the XRT needs a shell loading by xsabin file,  we also refer the script "create_xsabin.sh" provided by XRT deb package.
    only give the mcs file(without giving uuid info) => xclbinxuil --add-section MCS-PRIMARY:RAW:myZCU106.mcs --output myZCU106.xsabin
    and program the xsabin file manually  => xbmgmt partition --program --name myZCU106.xsabin
    Nevertheless, it shows the error below:

[xbmgmt] ERROR: Can not get BLP interface uuid. Please make sure corresponding BLP package is installed.: Invalid argument

  we have no idea about the BLP package...

We have some questions as below:

1. What would be the recommended approach to successfully pass through the XRT path on ZCU106?
2. Alternatively, would you suggest using a different class ID to switch the initialization flow ?

thanks for your assistance.

[christinayao]

Sorry, since I can't successfully upload the photo about the issue 1, below is my deeper descriptions.

I can only give the following values through debug bridge:

1. PCIe XVC VSEC Base Address
2. PCIe XVC VSEC Length
3. PCIe XVC VSEC Next pointer
4. PCIe XVC VSEC ID
5. PCIe XVC VSEC Rev ID

However, I don't find somewhere to give the value of PF offset and uuid.