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YS_Chen1024
Journeyman III
3 weeks ago

Use "cortex a72" in VMK180 for a bare-metal application, do "mov SP, X0" at EL1 occurs exception.

Hi:

    I am a beginner of the ARM cortex A72 processor.

    We would develop a bare-matal application on the VMK180 evaluation board using cortex A72.

 

    I am trying to modify the boot.S in the BSP of the stand-alone domain.

    My flow is:

       ==> change from EL3 to EL2; and then from EL2 to EL1.

       ==> Only at EL1, and after I set the VBAR_EL1, I do "mov SP, X0" and it occurs a synchronous exception error. /*note: it is confirmed the "X0" register is 16-byte aligned*/ 

              I can't even access the ESR_ELx because it also occurs exception.

              So I have no idea why this problem occurs. Could someone help me?

             Thank you.

 

      

 

    

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Krotti83
Journeyman III
3 weeks ago

Hi!

 

@YS_Chen1024 wrote:
[...]

       ==> change from EL3 to EL2; and then from EL2 to EL1.

       ==> Only at EL1, and after I set the VBAR_EL1, I do "mov SP, X0" and it occurs a synchronous exception error. /*note: it is confirmed the "X0" register is 16-byte aligned*/ 

              I can't even access the ESR_ELx because it also occurs exception.

              So I have no idea why this problem occurs. Could someone help me?

             Thank you.

    

Changing from EL3->EL2-EL1 is successful?

What do mean with "X0 register is 16-byte aligned"? Do you mean the previous loaded content (stack top address) in x0? Typo?

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