The test found that the core frequency of the ZEN2 processor CCX is uniform, or there is a floating of 25/50/100Mhz.
Manually set different frequencies for different cores in CCX. If there is a high probability, the core frequency will fall to a lower level. If there is no problem setting the unified frequency.
At the same time, it is found that the core of CCX can be set to the highest core frequency of the main frequency.
0.44441717791411
0.4998773006135
0.57128834355828
0.66650306748466
0.79975460122699
Whether these ratios are related to PLL design or clock tree planning, that is, there is only one PLL in each CCX, but it seems to be incompatible with 25/50/100Mhz offset (clock stretch?), how to set the AMD ZEN2 processor clock tree, What is special or purpose?
