vivado 2018.3 QDRII+ SRAM IP core simulation in default setting of example project is wrong, I find c0_init_calib_complete is valid very soon, but I think the memory calibration is not done, because I don't find the calibration process in data bus. And I find the read data(app interface) is not the same as the write data, the read data shift one word to the write data.
I use ISE14.7 MIG IP core(use QDRII+ SRAM) to simulate in default setting of example project, I find init_calib_complete is valid after a moment, and I think the memory calibration is done, because I find the calibration process in data bus. And I find the read data(app interface) is the same as the write data.
Who can answer that the simulation result of two platforms is not the same?
