Drivers & Software

[eqshodz]

When a driver submits work to the command queue ring buffer that is on System RAM, and the driver informs the GPU that there is a new work through MMIO register, how does the GPU read the new command in the command queue ring buffer. Does the GPU raise an interrupt for a DMA to read the command in, or does the GPU read the command queue directly using a IOMMU?

[elstaci]

If you don't get many answer here and you sound like a developer or engineer try also posting at AMD Developer's Forum but start here first to get permission: https://community.amd.com/t5/newcomers-start-here/bd-p/newcomer-forum

[nababweb]

how does the GPU read the new command in the command queue ring buffer. Does the GPU raise an interrupt for a DMA to read the command in, or does the GPU read the command queue directly using a IOMMU?