AMD 7 Series device lifecycles extended through 2040

AMD UltraScale+™ device lifecycles extended through 2045

AMD Versal™ adaptive SoCs available through 2045+

(All temperatures and speed grades, excluding HBM devices)

Last year, Xilinx has added a one-of-a-kind speed-demon to our production-proven Virtex® UltraScale+™ HBM FPGA family, VU57P, which integrates 16GB of HBM DRAM with 58G PAM4 transceivers, our high-performance FPGA fabric, and high-speed connectivity hard IP. The production version of the VU57P devices are shipping now.

Learn how Xilinx helped power the NASA Perseverance Rover's successful voyage to Mars. 

Many application domains that were bottlenecked in the past by insufficient compute power have been significantly advanced by the development of heterogeneous computing accelerators like the UltraScale™ devices, UltraScale+™ devices, and Versal™ ACAPs . Examples of popular heterogeneous compute-accelerated workloads in today's Data Centers are artificial intelligence, live video transcoding, and genomic analytics, to name just a few. Virtex UltraScale+ HBM FPGAs provide unparalleled adaptability and compute acceleration to modern data-center workloads.

Xilinx has introduced the Virtex® UltraScale+™ 56G PAM4 VCU129 FPGA evaluation kit to enable the design of a next-generation networking platform, bringing unparalleled adaptability and performance. Virtex UltraScale+ 58G PAM4 FPGAs are built upon the same building blocks used by the Xilinx 16nm UltraScale+ FPGA family and have integrated PAM4 transceiver, KP4 FEC, 100GE, and 150G Interlaken blocks. The PAM4 transceivers in these Virtex UltraScale+ FPGAs are another great example of Xilinx’s transceiver technology leadership. With a variety of 56G interfaces on the VCU129 evaluation kit, designers can evaluate upcoming optics, cables, and protocols to build a future-proofing platform while preserving their existing investment.

As previously noted in our PAM4 Technology at DesignCon - Part 1 blog, Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. Today, we're going to talk about demos with Samtec and TE.

In addition to great demos at DesignCon, Xilinx showcased Virtex® UltraScale+™ FPGAs at OFC 2019.

FlexEthernet (FlexE) is a new flexible Ethernet client interface standard defined by the OIF. FlexE specifies ways to support Ethernet MAC rates that don't correspond exactly to those in the IEEE's Ethernet specifications. FlexE supports a various Ethernet MAC rates such as 10G, 40G, and nx25G. Using FlexE enables network operators to decouple Ethernet rates on the client side from the actual physical interface via a new shim, packaging multiple Ethernet streams of 5, 10, 25 or even 100G into a higher rate interface. This enables network planners to integrate newer faster interfaces with existing interconnect and infrastructure. FlexE also allows the use of lower rate Ethernet PHYs to be used to send larger rate Ethernet MAC rates using bonding.

DesignCon 2019 has come and gone, and with it came a flurry of new interconnects targeting a variety of forward-looking serial technology. Xilinx partnered with four connector vendors to present six demonstrations showing what architects can look forward to using in their designs. From the near term 32G PCIe® style and emerging 58Gb/s PAM4 long reach interconnects to tomorrow’s 112G PAM4 topologies, Xilinx had SerDes technologies on display to fit everyone’s next generation wish list. In the following two weeks, we are going to release a series of Xilinx PAM4 technology demos from DesignCon. Stay tuned!