Archives Discussions

[zpdixon]

The RV670 has 64 SPUs total: 4 SIMD engines with 16 SPUs each. The RV770 has 160 SPUs total: out of curiosity, how are they organized, 4 SIMD engines x 40 SPUs ?

[rahulgarg]

10 rows of 16 SPUs each as far as i am aware.

[rafal_lewczuk]

Originally posted by: zpdixon The RV670 has 64 SPUs total: 4 SIMD engines with 16 SPUs each. The RV770 has 160 SPUs total: out of curiosity, how are they organized, 4 SIMD engines x 40 SPUs ?

Here is something about RV770 architecture.

http://www.tomshardware.com/reviews/radeon-hd-4850,1957.html

Regards,

rle

[zpdixon]

Excellent article, thanks ! Although I have i386/amd64/cell assembly experience, I am new to GPGPU computing and am suddendly discovering the potential of GPUs... This is just amazing. I am ordering an HD 4850 right now. The Tom's hardware article mentions that contrary to the R600 family, R700 GPUs are capable of executing binary shift instructions on all 5 ALUs (X, Y, Z, W, Trans). I presume this is documented in the R700 ISA specs, but where can I find them ? AMD only released the R600 ISA specs so far.

[zpdixon]

Look at that there is even a Local Data Share thing ! So reminiscent of the Cell SPU Local Data Stores... Oh my gosh, I can't wait to start coding 🙂