1 Reply Latest reply on Dec 21, 2007 11:31 PM by pdrongowski

    Why does L1 misses  != L2 requests?

      Hey all,

      Im using a hardware profiler to record the number of cache events. Specifically i record, the number of L1 cache hits on the instruction and data cache and the number of L2 requests and hits.

      My assumption is that the total numebr of L1 cahce misses should be the same as the total number of L2 requests. However, after i examine the results from running my profiling the number of L1 misses is roughly 10 times smaller than the number of L2 requests.

      This obviously seems very wrong...

      Does anyone have any pointers?



      p.s. this is a repost from the general forum, i'm sorry for the duplicate repost
        • Why does L1 misses  != L2 requests?
          Hi Matt --

          The L2 cache also services page table lookups for the TLBs. The "Requests to L2 Cache" event has unit mask values that can be used to breakdown the requests into IC fill, DC fill, and TLB fill.

          The "BIOS and Kernel's Developer Guide" or "BKDG" is the best place to look for descriptions of the performance counter events. You'll need to get the BKDG for the particular AMD processor on which you're taking measurements. The BKDGs are available in the Documentation section of AMD Dev Central.

          -- pj