cheka

Why does L1 misses  != L2 requests?

Discussion created by cheka on Dec 7, 2007
Latest reply on Dec 21, 2007 by pdrongowski
Hey all,

Im using a hardware profiler to record the number of cache events. Specifically i record, the number of L1 cache hits on the instruction and data cache and the number of L2 requests and hits.

My assumption is that the total numebr of L1 cahce misses should be the same as the total number of L2 requests. However, after i examine the results from running my profiling the number of L1 misses is roughly 10 times smaller than the number of L2 requests.

This obviously seems very wrong...

Does anyone have any pointers?

Thanks

Matt

p.s. this is a repost from the general forum, i'm sorry for the duplicate repost

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