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Hi Matt --
The L2 cache also services page table lookups for the TLBs. The "Requests to L2 Cache" event has unit mask values that can be used to breakdown the requests into IC fill, DC fill, and TLB fill.
The "BIOS and Kernel's Developer Guide" or "BKDG" is the best place to look for descriptions of the performance counter events. You'll need to get the BKDG for the particular AMD processor on which you're taking measurements. The BKDGs are available in the Documentation section of AMD Dev Central.
Thanks for the reply.
I shall read the documentation you mention. However, the number of L2 requests is almost 10x the number of L1 misses. This number seems a little high