Is there a possibility to invalidate TLB entries on another CPU?
I use many threads in the same Addressspace. Due to the application design i have to page in and out a lot. Every time i do so the TLB of my thread and the other threads need to be invalidated. Is there another way to invalidate the TLBs / particular entries in the TBL without sending an Interrupt to all affected CPUs?
I'd like to send a INVLPG throuch the APIC to another CPU without disrupting their work.
for a quadcore it maybe was ok, but if i have in the future 64 cores running and everys time i change a page the cores have to invaldiate that page by hand in 64 CPUs or - even worse - flush the whole TLB then i expect a better solution.