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Is the I/O chip considered a chiplet or not?

Question asked by neon on Jan 26, 2019

This may seem pedantic, but I am writing something and would like to get this correct. 

Is the I/O chip in the upcoming implementation of Epyc (Rome) considered a "chiplet"? In other words, will AMD refer to Rome as an 8-chiplet design or a 9-chiplet design?

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