To my knowledge, Ryzen can only manage 16 FLOPS per cycle (same as older 15h architecture).
To me this is the biggest weakness of the new kid in town.
Now the enemy's Skylake can do 32 per cycle and Knights Landing 64 per cycle.
Intel talks up its use of 256-bit and 512-bit FMACs compared with AMD’s 128-bit implementation of AVX. But AMD may have taken the wiser route here (it wins all the FPU benchmarks AT ran). Intel takes a 20 percent clock penalty compared with 256-bit AVX when running AVX-512. While higher efficiency should theoretically be able to still show significant AVX-512 performance improvements, they’re only going to happen with substantial performance tuning. Not all software vendors or buyers can afford that kind of work, but it’ll be critical for AVX-512 to be a success.
AMD Epyc Faces Off With Intel Skylake-SP Xeon in Massive Server Battle - ExtremeTech
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