5-Level Paging and 57-bit Linear Address? Stop that stupid!

Discussion created by mr.unknown on Jun 11, 2017
Latest reply on Apr 24, 2020 by chaoscode

In Intel's 5-Level Paging and 5-Level EPT white paper, they planed to introduce another level paging mechanism, PML5, extending the linear address from 48-bit to 57-bit (57-bit, not 64-bit!!!!!). What that stupid thing that I find on earth! Adding a level to current paging system is easy and simple, but the overheads it brings do really waste the treasurable memory resources in doing nothing at all, but increase the power consumption too. Are they really make it innovative or another experimental product letting the end consumers to pay for the bill? Remember Intel Pentium 4 processors? For their poor performance, but incredible power hunger and heat producing? Stupid NetBurst microarchitecture consumed too lot of energies but almost doing nothing at all, but people then paid lot of money onto them, and they might just only paid for the costs while they do research on the Intel Core microarchitecture.


What about AMD? I love AMD64 processors, because the AMD64 architecture is a practical and feasible architecture meeting today's needs. This architecture also provided the back-ward support for the legacy x86 software in the compatibility and Legacy mode. If future AMD64 processors with Legacy Mode eliminated, then it would get rid of lots of limitations. I wish AMD64 architecture is a smart and smarter architecture, I wish the AMD architects would use some other smarter ways to implement future paging mechanism, rather than merely introducing additional paging level.