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Explanation of terms from chapter 9 of GCN ISA manual

Question asked by ocelverde on Mar 22, 2017
Latest reply on Mar 23, 2017 by dipak



I am not allowed to post in the HSA section (or is there a GCN/ROCm section?), hopefully someone knowledgeable will find the question here.


Chapter 9 of GCN ISA Manual (the version from August 2016) on flat memory instructions uses a number of terms that are not explained anywhere in the document.  Specifically, I am confused by the following:


1) scratch space - what exactly is the difference between LDS and scratch space?  Is scratch space a part of LDS that is private to a wavefront?  Or to a an OpenCL "thread"?  or something completely separate and independent?  (Is it at least usually in LDS then?)


2) TA - this looks like reference to global memory, or system memory on an APU, or something like that.  But then, TA appears also in section 8 where various strange references to it (for a CPU guy like me, the whole section 8 is just completely cryptical and I am never sure I really understand anything) suggest it has an active role in computing various address parts.  Moreover, in section 9.3, TA also modifies the address, so it cannot be just memory but rather some gateway to it.  This is very confusing.  Also, 9.3 suggests that scratch is outside of LDS, which is counterintuitive.  Please at least define the acronym TA somewhere.


3) aperture(s) - I suppose this means area(s) in the virtual addressed space that are somehow mappeed to some real memory.  But a definition or a nice explanation of the term (and how many there are, who sets them up and how), would be very welcome.


I would be grateful for any explanation of these terms.  The buffered memory accesses seem too complicated for computing and would like to use flat instructions instead, also for LDS and stuff.