0 Replies Latest reply on Jan 25, 2017 10:32 AM by sdconsta

    AMD Pacifica, Problem with I/O and SL_DEV

    sdconsta

      I'm playing with the skinit instruction, and I'm experiencing some unexpected behavior that I cannot diagnose. From the AMD Pacifica Specification, Section 2.19.8:

       

      "The host bridge contains additional logic that operates in conjunction with the SKINIT instruction to provide a limited form of memory protection during the secure startup protocol. This provides protection for a Secure Loader image in memory, allowing it to, among other things, set up full DEV protection. (See section 3.1.6 on page 57 for detailed operation of SKINIT.) The host bridge logic includes a hidden (not accessible to software) SL_DEV_BASE address register. SL_DEV_BASE points to a 64KB-aligned 64KB region of physical memory. When SL_DEV_EN is 1, the 64KB region defined by SL_DEV_BASE is protected from external access (as if it were protected by the DEV), as well as from any access (both CPU and external accesses) via GART-translated addresses. Additionally, the SL_DEV mechanism, when enabled, blocks all device accesses to PCI Configuration space."

       

      The program I'm testing is a kind of bootloader which uses color VGA (e.g. 0xb8000) for text output. Before skinit, my VGA output works fine. After skinit, all VGA output is being suppressed until I clear the SL_DEV_EN bit, at which point I can resume VGA output as normal. What I don't understand is why the output is being suppressed, given the text from the Pacifica specification. My 64KB SLB is being loaded at 0x100000, which does not overlap with the VGA space, so I don't think that the DEV protections should affect the VGA space.