I'm making Displayport Rx in my company and now testing with FPGA and Radeon Displayport Tx.
My test is stuck in Link Training Pattern: after the Rx updates that all Link Training are passed (CR-lock, EQ-lock, Symbol-lock, and Align-done) on DPCD and replies them to Tx through AUX, Tx turns on a power save mode through AUX, then starts 1-lane RBR training after finishing power save mode.
Which case can make the Tx to enter the power save mode just after finishing the Link Training? Is this sequence correct?
Also, I am curious that why Tx starts retraining for 1-lane RBR after power save even if my Rx passed a 2-lane HBR training before.
HPD was asserted and fixed to '1' until the end.
Any comments will be helpful!